MOC2030

MOC2030, Elektronika, elementy

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SEMICONDUCTOR APPLICATION NOTE
Order this document
by AN982/D
Prepared by Horst Gempe
INTRODUCTION
presence. Brief examples of typical applications are pres-
ented.
The zero–cross family of optically isolated triac drivers in an
inexpensive, simple and effective solution for interface ap-
plications between low current dc control circuits such as logic
gates and microprocessors and ac power loads (120, 240 or
380 volt, single or 3–phase).
These devices provide sufficient gate trigger current for high
current, high voltage thyristors, while providing a guaranteed
7.5 kV dielectric withstand voltage between the line and the
control circuitry. An integrated, zero–crossing switch on the
detector chip eliminates current surges and the resulting elec-
tromagnetic interference (EMI) and reliability problems for
many applications. The high transient immunity of 5000 V/
m
s,
combined with the features of low coupling capacitance, high
isolation resistance and up to 800 volt specified V
DRM
ratings
qualify this triac driver family as the ideal link between sensi-
tive control circuitry and the ac power system environment.
Optically isolated triac drivers are not intended for stand
alone service as are such devices as solid state relays. They
will, however, replace costly and space demanding discrete
drive circuitry having high component count consisting of
standard transistor optoisolators, support components includ-
ing a full wave rectifier bridge, discrete transistors, trigger
SCRs and various resistor and capacitor combinations.
This paper describes the operation of a basic driving circuit
and the determination of circuit values needed for proper im-
plementation of the triac driver. Inductive loads are discussed
along with the special networks required to use triacs in their
CONSTRUCTION
The zero–cross family consists of a liquid phase EPI, in-
frared, light emitting diode which optically triggers a silicon
detector chip. A schematic representation of the triac driver
is shown in Figure 1. Both chips are housed in a small, 6–pin
dual–in–line (DIP) package which provides mechanical in-
tegrity and protection for the semiconductor chips from exter-
nal impurities. The chips are insulated by an infrared
transmissive medium which reliably isolates the LED input
drive circuits from the environment of the ac power load. This
insulation system meets the stringent requirements for isola-
tion set forth by regulatory agencies such as UL and VDE.
THE DETECTOR CHIP
The detector chip is a complex monolithic IC which contains
two infrared sensitive, inverse parallel, high voltage SCRs
which function as a light sensitive triac. Gates of the individual
SCRs are connected to high speed zero crossing detection
circuits. This insures that with a continuous forward current
through the LED, the detector will not switch to the conducting
state until the applied ac voltage passes through a point near
zero. Such a feature not only insures lower generated noise
(EMI) and inrush (Surge) currents into resistive loads and
moderate inductive loads but it also provides high noise immu-
nity (several thousand V/
m
s) for the detection circuit.
MT
ZERO
CROSSING
DETECTOR
I
F
ZERO
CROSSING
DETECTOR
MT
DETECTOR
LED
Figure 1. Schematic of Zero Crossing Optically Isolated Triac Driver
REV 1
Motorola Optoelectronics Device Data
Motorola, Inc. 1995
1
W
ON STATE
Q1
BLOCKING
STATE
A
2
+
I
DRM
I
H
V
DRM
V
DRM
I
MT
I
F
V
ZERO
CROSSING
DETECTOR
V
F
V
A
2
–
I
H
–
I
I
DRM
MT
BLOCKING STATE
Q111
ON STATE
Figure 2. Simplified Schematic of Isolator
Figure 3. Triac Voltage–Current Characteristic
ELECTRICAL CHARACTERISTICS
must be used to prevent false “turn on” of the main triac. A de-
tailed discussion of a “snubber” network is given under the
section “Inductive and Resistive Loads.”
Figure 4 shows a static dV/dt test circuit which can be used
to test triac drivers and power triacs. The proposed test meth-
od is per EIA/NARM standard RS–443.
Tests on the MOC3061 family of triac drivers using the test
circuit of Figure 4 have resulted in data showing the effects of
temperature and voltage transient amplitude on static dV/dt.
Figure 5 is a plot of dV/dt versus ambient temperature while
Figure 6 is a similar plot versus transient amplitude.
A simplified schematic of the optically isolated triac driver is
shown in Figure 2. This model is sufficient to describe all im-
portant characteristics. A forward current flow through the
LED generates infrared radiation which triggers the detector.
This LED trigger current (I
FT
) is the maximum guaranteed cur-
rent necessary to latch the triac driver and ranges from 5 mA
for the MOC3063 to 15 mA for the MOC3061. The LED’s for-
ward voltage drop at I
F
= 30 mA is 1.5 V maximum. Voltage–
current characteristics of the triac are identified in Figure 3.
Once triggered, the detector stays latched in the “on state”
until the current flow through the detector drops below the
holding current (I
H
) which is typically 100
m
A. At this time, the
detector reverts to the “off” (non–conducting) state. The detec-
tor may be triggered “on” not only by I
FT
but also by exceeding
the forward blocking voltage between the two main terminals
(MT1 and MT2) which is a minimum of 600 volts for all
MOC3061 family members. Also, voltage ramps (transients,
noise, etc.) which are common in ac power lines may trigger
the detector accidentally if they exceed the static dV/dt rating.
Since the fast switching, zero–crossing switch provides a
minimum dV/dt of 500 V/
m
s even at an ambient temperature
of 70
°
C, accidental triggering of the triac driver is unlikely. Ac-
cidental triggering of the main triac is a more likely occurrence.
Where high dV/dt transients on the ac line are anticipated, a
form of suppression network commonly called a “snubber”
BASIC DRIVING CIRCUIT
Assuming the circuit shown in Figure 7 is in the blocking or
“off” state (which means I
F
is zero), the full ac line voltage ap-
pears across the main terminals of both the triac and the triac
driver. When sufficient LED current (I
FT
) is supplied and the ac
line voltage is below the inhibit voltage (I
H
in Figure 3), the triac
driver latches “on.” This action introduces a gate current in the
main triac triggering it from the blocking state into full conduc-
tion. Once triggered, the voltage across the main terminals
collapses to a very low value which results in the triac driver
output current decreasing to a value lower than its holding cur-
rent, thus forcing the triac driver into the “off” state, even when
I
FT
is still applied.
15 V
HV
SCOPE PROBE 100:1
1
0
W
150 k
W
1
0 k
P8
–15 V
1
00
W
MERCURY
WETTED
RELAY
0.001
m
F
DUT
SIGN
A
L IN
470
W
HV
0.63HV
HV
VOLTAGE APPLIED TO DUT –
0
5
0% DUTY CYCLE
0
16 ms
t
RC
TEST PROCEDURE –
Turn the D.U.T. on, while applying sufficient dV/dt to ensure that it remains on, even after the trigger current is re-
moved. Then decrease dV/dt until the D.U.T. turns off. Measure
t
RC
, the time it takes to rise to 0.63 HV, and divide 0.63
HV by
t
RC
to get dV/dt.
Figure 4. Static dV/dt Test Circuit
2
Motorola Optoelectronics Device Data
10000
600
TRANSIENT AMPLITUDE
= 600 V
5000
2000
1000
500
25
50
75
100
100
200
300
400
500
600
T
A
, AMBIENT TEMPERATURE (
°
C)
TRANSIENT AMPLITUDE (V)
Figure 5. Static dV/dt versus Temperature
Figure 6. Static dV/dt versus Transient Amplitude
The power triac remains in the conducting state until the
load current drops below the power triac’s holding current, a
situation that occurs every half cycle. The actual duty cycle for
the triac driver is very short (in the 1 to 3
m
s region). When I
FT
is present, the power triac will be retriggered every half cycle
of the ac line voltage until I
FT
is switched “off” and the power
triac has gone through a zero current point. (See Figure 8).
Resistor R (shown in Figure 7) is not mandatory when R
L
is
a resistive load since the current is limited by the gate trigger
current (I
GT
) of the power triac. However, resistor R (in com-
bination with R–C snubber networks that are described in the
section “Inductive and Resistive Loads”) prevents possible
destruction of the triac driver in applications where the load is
highly inductive.
Unintentional phase control of the main triac may happen if
the current limiting resistor R is too high in value. The function
of this resistor is to limit the current through the triac driver in
case the main triac is forced into the non–conductive state
close to the peak of the line voltage and the energy stored in
a “snubber” capacitor is discharged into the triac driver. A cal-
culation for the current limiting resistor R is shown below for
a typical 220 volt application: Assume the line voltage is 220
volts RMS. Also assume the maximum peak repetitive driver
current (normally for a 10 micro second maximum time inter-
val) is 1 ampere. Then
I
peak
220 2
volts
R
311 ohms
1 amp
One should select a standard resistor value >311 ohms
330 ohms.
The gate resistor R
G
(also shown in Figure 7) is only neces-
sary when the internal gate impedance of the triac or SCR is
very high which is the case with sensitive gate thyristors.
These devices display very poor noise immunity and thermal
stability without R
G
. Value of the gate resistor in this case
should be between 100 and 500. The circuit designer should
be aware that use of a gate resistor increases the required trig-
ger current (I
GT
) since R
G
drains off part of I
GT
. Use of a gate
resistor combined with the current limiting resistor R can result
in an unintended delay or phase shift between the zero–cross
point and the time the power triac triggers.
I
FT
I
F
T
1
6
R
MT2
AC LINE
VOLTAGE
2
5
AC
INPUT
TRIAC DRIVER
CURRENT
I = I
GT
+ I
I
3
ZERO
CROSSING
CIRCUIT
4
I
GT
I
I
I
L
R
G
MT1
R
L
V – ACROSS
MAIN TRIAC
TRIAC DRIVER
POWERTRIAC
I
L
Figure 7. Basic Driving Circuit — Triac Driver,
Triac and Load
Figure 8. Waveforms of a Basic Driving Circuit
Motorola Optoelectronics Device Data
3
V
peak
UNINTENDED TRIGGER DELAY TIME
2000
To calculate the unintended time delay, one must remember
that power triacs require a specified trigger current (I
GT
) and
trigger voltage (V
GT
) to cause the triac to become conductive.
This necessitates a minimum line voltage V
T
to be present be-
tween terminals MT1 and MT2 (see Figure 7), even when the
triac driver is already triggered “on.” The value of minimum line
voltage V
T
is calculated by adding all the voltage drops in the
trigger circuit:
V
T
= V
R
+ V
TM
+ V
GT
.
Current I in the trigger circuit consists not only of I
GT
but also
the current through R
G
:
I
=
I
R
G
+
I
GT.
Likewise, I
R
G
is calculated by dividing the required gate trig-
ger voltage V
GT
for the power triac by the chosen value of gate
resistor R
G
:
I
R
G
=
V
GT
/R
G
Thus, I = V
GT
/R
G
+ I
GT
.
All voltage drops in the trigger circuit can now be determined
as follows:
V
R
= I
R = V
GT
/R
G
R + I
GT
R = R(V
GT
/R
G
+ I
GT
)
VTM = From triac driver data sheet
V
GT
= From power triac data sheet.
I
GT
= From power triac data sheet.
With V
TM
, V
GT
and I
GT
taken from data sheets, it can be seen
that V
T
is only dependent on R and R
G
.
Knowing the minimum voltage between MT1 and MT2 (line
voltage) required to trigger the power triac, the unintended
phase delay angle
200
0
300 500
1000
1500
2000
R (OHMS)
Figure 9. Time Delay t
d
versus Current Limiting Resistor R
SWITCHING SPEED
q
d
(between the ideal zero crossing of the
ac line voltage and the trigger point of the power triac) and the
trigger delay time t
d
can be determined as follows:
d
sin-1 V
T
V
peak
The switching speed of the triac driver is a composition of
the LED’s turn on time and the detector’s delay, rise and fall
times. The harder the LED is driven the shorter becomes the
LED’s rise time and the detector’s delay time. Very short I
FT
duty cycles require higher LED currents to guarantee “turn on”
of the triac driver consistent with the speed required by the
short trigger pulses.
Figure 10 shows the dependency of the required LED cur-
rent normalized to the dc trigger current required to trigger the
triac driver versus the pulse width of the LED current. LED trig-
ger pulses which are less than 100
sin-1
R(V
GT
R
G
I
GT
)
V
TM
V
GT
V
peak
s in width need to be high-
er in amplitude than specified on the data sheet in order to
assure reliable triggering of the triac driver detector.
The switching speed test circuit is shown in Figure 11. Note
that the pulse generator must be synchronized with the 60 Hz
line voltage and the LED trigger pulse must occur near the
zero cross point of the ac line voltage. Peak ac current in the
curve tracer should be limited to 10 mA. This can be done by
setting the internal load resistor to 3 k ohms.
m
q
Vpeak
(which is 90 de-
grees) multiplied by the time it takes the line voltage to go from
zero voltage to peak voltage (simply 1/4f, where f is the line fre-
quency). Thus
t
d
=
q
d
/90
1/4f.
Figure 9 shows the trigger delay of the main triac versus the
value of the current limiting resistor R for assumed values of
I
GT
. Other assumptions made in plotting the equation for t
d
are
that line voltage is 220 V RMS which leads to V
peak
= 311 volts;
R
G
= 300 ohms; V
GT
= 2 volts and f = 60 Hz. Even though the
triac driver triggers close to the zero cross point of the ac volt-
age, the power triac cannot be triggered until the voltage of the
ac line rises high enough to create enough current flow to latch
the power triac in the “on” state. It is apparent that significant
time delays from the zero crossing point can be observed
when R is a large value along with a high value of I
GT
and/or
a low value of R
G
. It should be remembered that low values of
the gate resistor improve the dV/dt ratinigs of the power triac
and minimize self latching problems that might otherwise oc-
cur at high junction temperatures.
q
d
to
4
Motorola Optoelectronics Device Data
The time delay t
d
is the ratio of
Motorola isolated triac drivers are trigger devices and de-
signed to work in conjunction with triacs or reverse parallel
SCRs which are able to take rated load current. However, as
soon as the power triac is triggered there is no current flow
through the triac driver. The time to turn the triac driver “off” de-
pends on the switching speed of the triac, which is typically on
the order of 1–2
m
s.
25
20
NORMALIZED TO:
PW IN
100
m
s
15
10
5
1
0
1
2
5
10
20
50
100
LED TRIGGER PULSE WIDTH (
m
s)
Figure 10. I
FT
Normalized to I
FT
dc As Specified on the
Data Sheet
PULSE WIDTH CONTROL
DELAY CONTROL
AMPLITUDE CONTROL
DUT
1
6
R
L
PULSE
GENERATOR
10
W
2
5
3
ZERO
CROSSING
CIRCUIT
4
CURVE
TRACER (AC MODE)
AC LINE
SYNC
I
F
MONITOR
SCOPE
Figure 11. Test Circuit for LED Forward Trigger Current versus Pulse Width
INDUCTIVE AND RESISTIVE LOADS
only 0.13 V/
m
s for a 240 V, 50 Hz line source and 0.063 V/
m
s
for a 120 V, 60 Hz line source. For inductive loads the “turn off”
time and commutating dV/dt stress are more difficult to define
and are affected by a number of variables such as back EMF
of motors and the ratio of inductance to resistance (power fac-
tor). Although it may appear from the inductive load that the
rate or rise is extremely fast, closer circuit evaluation reveals
that the commutating dV/dt generated is restricted to some fi-
nite value which is a function of the load reactance L
L
and the
device capacitance C but still may exceed the triac’s critical
commuting dV/dt rating which is about 50 V/
m
s. It is generally
good practice to use an RC snubber network across the triac
to limit the rate of rise (dV/dt) to a value below the maximum
allowable rating. This snubber network not only limits the volt-
age rise during commutation but also suppresses transient
voltages that may occur as a result of ac line disturbances.
There are no easy methods for selecting the values for R
s
and C
s
of a snubber network. The circuit of Figure 13 is a
damped, tuned circuit comprised of R
s
, C
s
, R
L
and L
L
, and to
a minor extent the junction capacitance of the triac. When the
triac ceases to conduct (this occurs every half cycle of the line
voltage when the current falls below the holding current), the
Inductive loads (motors, solenoids, etc.) present a problem
for the power triac because the current is not in phase with the
voltage. An important fact to remember is that since a triac can
conduct current in both directions, it has only a brief interval
during which the sine wave current is passing through zero to
recover and revert to its blocking state. For inductive loads, the
phase shift between voltage and current means that at the
time the current of the power handling triac falls below the
holding current and the triac ceases to conduct, there exists
a certain voltage which must appear across the triac. If this
voltage appears too rapidly, the triac will resume conduction
and control is lost. In order to achieve control with certain in-
ductive loads, the rate of rise in voltage (dV/dt) must be limited
by a series RC network placed in parallel with the power triac.
The capacitor C
s
will limit the dV/dt across the triac.
The resistor R
s
is necessary to limit the surge current from
C
s
when the triac conducts and to damp the ringing of the ca-
pacitance with the load inductance L
L
. Such an RC network is
commonly referred to as a “snubber.”
Figure 12 shows current and voltage wave forms for the
power triac. Commutating dV/dt for a resistive load is typically
Motorola Optoelectronics Device Data
5
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